This invention relates to techniques for electrically isolating semiconductor devices and components in monolithic integrated circuits. In particular, the invention is a method for forming void-free, planarized dielectric trench structures. The method uses doped oxide reflow to provide a void-free planar isolation layer and a multiple underlayer which functions as an etch stop and dopant/oxidation barrier.
Dielectric isolation techniques have been the preferred technology for isolating integrated circuits and their constituent devices and elements, at least in part because of the ability to closely pack the isolation dielectric and the circuit elements. Integrated circuit isolation by the so-called local oxidation of silicon (LOCOS) has been known for a number of years, as have the attendant problems. The well-known limitations of the LOCOS process include at least three factors which may constrain the process from applicability to future small geometry, highly dense LSI and VLSI structures. These limitations are, first, the formation of the so-called bird's beak oxide configuration and the associated encroachment of the field oxide beneath the oxidation mask. Encroachment by the bird's beak oxide limits the percentage of chip surface area which is available for device formation. Secondly, the limited thickness results in undesirably high circuit capacitances. Third, the characteristic non-planar surface topography makes it difficult to perform the increasingly high resolution photolithographic operations which are required to fabricate VSLI circuits. In turn, the decreased resolution increases the minimum feature sizes and minimum tolerances and, as a consequence, decreases the achievable device densities.
The use of LOCOS isolation has persisted, however, because of the past shortcomings of the available substitute isolation technologies. Typical trench isolation processes involve etching grooves about 1 to 6 microns deep into the semiconductor substrate, filling the grooves with a suitable dielectric and performing a planarization operation. The dielectric material typically is undoped silicon dioxide or polysilicon. Typical prior art approaches are discussed, for example, in Rung, Momose and Nagakubo, "Deep Trench Isolated CMOS Devices", IEDM 82, pp. 237-240. The Rung et al. article discusses a trench isolation process which involves oxidizing the silicon substrate trench sidewalls, filling the trench with polysilicon or deposited oxide, etching the poly/oxide, then capping the structure with oxide. Another typical trench isolation approach is described in the article "A New Bird's-Beak Free Field Isolation Technology For VLSI Devices", by Kurosawa, Shibata and Iizuka, IEDM 81, pp. 384-387. The Kurosawa et al. technique involves the selective etching of stressed silicon dioxide following confomal deposition, combined with a lift-off of the silicon dioxide over the active regions.
In particular, trench isolation technology has the inherent potential advantages of small width-to-depth ratios, relative process simplicity, well-defined vertical-wall isolation regions and surface planarity. Like other VSLI features, however, the width of isolation trenches must be scaled downward to near micron and even submicron size to achieve the densities required in VSLI and future monolithic integrated circuit technologies. Unfortunately, it becomes increasingly difficult to completely fill the narrow, yet relatively deep trench configurations which are used for VSLI isolation. The resulting tendency to form voids is well-known and is shown, for example, by the data of Bondur et al, U.S. Pat. No. 4,104,086. Bondur et al. discloses a process for eliminating voids by precisely tapering the walls of the trenches, which tapers vary in relation to the sizes of the trenches. FIG. 1 illustrates the data of Bondur et al., which show that for vertical side wall trenches, the deposited silicon dioxide forms negative sloping side walls and, thus, voids.
Several approaches have been proposed which have as their purpose the control or elimination of such voids.
For example, Riseman, U.S. Pat. No. 4,356,211, forms a composite dual-oxide trench isolation structure in which a first oxide layer is formed, then a layer of polysilicon is deposited, anisotrophically etched, and heavily doped at the upper edge of the trench to accelerate silicon dioxide formation at such upper edge. Thereby the voids are sealed by the differential oxidation rate of the polysilicon. Clearly the parameters of the Riseman process do not provide for applications in which trenches of varying dimension are being processed simultaneously.
The above-mentioned Bondur et al. U.S. Pat. No. 4,104,086 uses tapered trench sidewalls to control the depth of isolation oxide voids relative to the substrate surface in a silicon substrate which has a highly doped near-surface region. Briefly, the Bondur et al process involves (1) forming the trench to a tapered profile, as by the use of reactive ion etching (RIE); (2) growing a thin layer of thermal oxide in the trench outline; (3) depositing CVD oxide; (4) etching back the CVD oxide using RIE; and (5) optionally, annealing in steam at 900.degree. to 950.degree. C. to enhance the "quality" of the silicon dioxide. The data disclosed in the Bondur et al patent indicate the vertical walls (which, of course, are desirable for density and resolution) inherently product voids in the deposited silicon oxide (see FIG. 1 herein). Also, the voids are buried deeper in the oxide relative to the substrate surface as the trench width increases and the taper increases. Conversely, the voids are formed closer to the surface and to exposure by the planarization etch-back in the case of narrower, vertical grooves.
Sakurai, U.S. Pat. No. 4,404,735, discloses a process for forming trench isolation structures. Initially, dry etching such as plasma etching, reactive sputter etching or ion beam etching is used for form the trench. The trench is then covered with a thin layer of deposited silicon dioxide which is formed to a thickness of between 500 to 1,000 angstroms to prevent substrate heating by the subsequent laser reflow process, prevent doping of the substrate from the isolation layer, and to isolate the silicon isolation layer from the substrate. Next, a CVD layer is formed to a thickness which is less than the trench depth and less than one-half the trench width using silicon or doped glass (phosphosilicate glass, PSG). The PSG/silicon is subsequently reflowed by laser heating. Essentially, the Sakurai process is a laser reflow process for filling narrow trenches from a thin silicon or PSG layer. In other words, the trench-filling layer is formed to an initial shallow thickness within the trench and laser heating is used to redistribute material from outside the trenches into the trenches. Apparently, the 500 to 1,000 Angstrom thickness of the blocking silicon dioxide layer is critical in that a minimum thickness is required to perform the heat-shielding and dopant-blocking functions, while, presumably, a maximum thickness is necessary for consistency with the state depth and width dimensions.
In view of the above-discussed constraints and difficulties associated with conventional trench isolation processes and structures, it is an object of the present invention to provide a method for forming a trench isolation structure which is free of voids.
Another object of the present invention is to provide a method for forming such a trench isolation structure which has planar surface topography over the trenches as well as the active regions.
Still another object of the present invention is to provide a process for forming void-free trench isolation structures which are suitable for use in high density monolithic integrated circuit structures such as VLSI circuits.